Power converters of the AC-DC-AC type are widely used in motor drives and power supply applications. These AC-DC-AC converters consist of a rectifier-inverter system along with a DC voltage link. The DC link is normally equipped with a large electrolytic capacitor which provides the stiff ripple free DC bus voltage required for proper inverter operation. However, this DC link capacitor is a large, heavy, and expensive component which continues to be a matter of concern in the industrial environment. Moreover, the DC bus capacitor is the prime factor in degradation of system reliability. This has been the driving motivation for much work aimed at decreasing the required size of this DC link capacitor.
A number of techniques have been reported which have been aimed at the complete elimination of the link capacitor, or reduction in its size. The implementation of these methods have required significant changes in the well known, extremely simple, and reliable rectifier-inverter power circuit configuration, and have involved complex control circuitry with added concerns of system stability. Some implementations have even involved the use of expensive floating point digital signal processing elements. In general, these solutions are not applicable to low cost, high volume applications such as fans, blowers and pumps.
Pulse Width Modulation (PWM) techniques have long been used to improve the performance and reliability of power conversion devices. Within the past decade such devices have improved steadily, yet the capacitor size and expense issue, as well as the reliability issue have remained paramount. This invention provides another level of improvement in power conversion devices by unique modifications to the PWM technique.
PWM in its basic form as applied to power inverters is illustrated in FIG. 1, the schematic of a conventional three-phase voltage source inverter. The diode bridge rectifier circuit (components 151, 152, 153, and 154) receives its power input from the AC power source 140, and its output is partially filtered by means of the DC link capacitor 150. The phase A, phase B, and phase C inverter outputs are derived from the inverter configuration comprised of N-channel MOSFET transistors 100 to 102 and 110 to 112. These output signals appear at the three nodes 190, 191 and 192. Providing appropriate drive signals for the gates of transistors 100 to 102 and 110 to 112 is the key to generating proper inverter output voltage. Diodes 160 to 162 and 170 to 172 act to clip any occurrences of reverse voltage at the drain to source of the inverter transistors 100 to 102 and 110 to 112.
The basic PWM equations which relate to the inverter switching functions, essentially the gating signals at the gate of transistors 100 to 102 and 110 to 112 will now be described. Let SW1, SW2, and SW3 be the inverter switching functions. The Fourier series expansions of the switching functions can be written as: ##EQU1##
where .omega..sub.i is the inverter operating frequency. The switching function for any PWM scheme consists of the fundamental frequency component, (n=1), and higher order harmonics. For a ripple free dc bus voltage V.sub.i =V.sub.DC, the inverter line to neutral output voltages are given by: ##EQU2##
The line to line voltage at the inverter output is given by: ##EQU3##
From equation 3 it is clear that the output voltage contains only the fundamental and the higher order harmonics present in the switching function. However, ripple components in the DC bus voltage of the inverter will have an effect on the AC output voltage.
To understand the effect of the ripple component, consider a case in which the DC bus voltage is not ripple free, as is the case when a smaller capacitor is used in the DC link. Assume that the DC voltage contains sinusoidally varying component of frequency .omega..sub.t, and of magnitude kV.sub.DC. Then the inverter input voltage can be represented as:
V.sub.i =V.sub.DC (1+k sin .omega..sub.t t) [4]
The line to neutral inverter output voltage can be computed from equation 2 and is given by: EQU V.sub.i +L =V.sub.DC (1+k sin .omega..sub.t t) SW [5]
The inverter line to line voltage can be obtained from equations 3 and 5, and is given by: ##EQU4##
From equation 6 it is evident that the DC bus voltage variation has a significant affect on the output voltage, due to the appearance of lower order harmonics (.omega..sub.i -n.omega..sub.i) and (.omega..sub.i -n.omega..sub.i) not present in the switching function SW.
In order to counteract the DC bus voltage fluctuation, the PWM switching function needs to be altered so that a counter modulation is introduced in the inverter control. The modified switching function for the above described illustration would be: ##EQU5##
Using equation 5, the inverter line to neutral voltage then becomes: EQU Vn=V.sub.DC (1+k sin .omega..sub.t t) SW.sub.new [8]
Substituting SW.sub.new from equation 7 into equation 8, gives: EQU V.sub.n =V.sub.DC.times.SW [9]
Equation 9 represents the inverter line to line voltage with a ripple component in the DC bus voltage. However, equation 9 is identical to equation 2, in which the DC bus voltage was assumed to be ripple free. Therefore, by employing the proposed technique, i.e. by suitably altering the inverter switching function (SW), immunity to the DC bus voltage ripple component can be achieved. In this invention the conventional space vector PWM technique is modified to meet that goal.
PRIOR ART:
Space Vector Pulse Width Modulation (PWM)
One of the most common methods of PWM is based on the `space vectors` of the inverter voltages. Space vectors of the line to neutral voltages are shown in FIG. 2. These eight vectors may be understood with reference to the eight inverter states described in Table 1. Each inverter state represents a single combination of the states of inverter switching transistors 100 to 102. Any one, two or all three of these transistors may be `on` in the eight possible combinations given in Table 1. The state of each of the complementary transistors 110 to 112 is the opposite. For example if transistor 100 is `on`, transistor 110 is `off`, and so on for transistor complementary pairs 101, the complement of 111, and transistor 102, the complement of transistor 112. The eight vectors of FIG. 2 relate to the instantaneous inverter states of Table 1.
TABLE 1 Eight Switching States of Voltage Source Inverter Transistor Transistor Transistor State 100 101 102 UPPER INVERTER TRANSISTORS 0 ON ON ON 1 OFF ON ON 2 ON OFF ON 3 OFF OFF ON 4 ON ON OFF 5 OFF ON OFF 6 ON OFF OFF 7 OFF OFF OFF LOWER INVERTER TRANSISTORS 7 ON ON ON 6 OFF ON ON 5 ON OFF ON 4 OFF OFF ON 3 ON ON OFF 2 OFF ON OFF 1 ON OFF OFF 0 OFF OFF OFF
Assume an arbitrary voltage .nu.* is to be generated by the three phase voltage source inverter of FIG. 1. The space vector PWM illustration of FIG. 2 shows the space vectors of the line to neutral voltages of such an inverter. The voltage source inverter of FIG. 2 can generate eight total states. Six of these states (.nu..sub.1 through .nu..sub.6) are non-zero vectors. The remaining vectors (.nu..sub.0 and .nu..sub.7) are zero states. They can occur only when all three upper (or lower) inverter switches are `on`. If only one transistor 100, 101 or 102, or any two transistors 100 and 101, or 101 and 102, or 102 and 103, are allowed to overlap in the `on` condition, only vectors .nu..sub.1 through .nu..sub.6 can be produced by the inverter and these vectors are termed as base vectors. The case of all three transistors 100, 101, and 102 `off`, or all three transistors 100, 101 and 102 `on` corresponds to the case of the null vectors .nu..sub.0 and .nu..sub.7.
The non-zero base vectors divide the cycle into six, 60.degree. wide sectors. The desired voltage .nu.*, located in any given sector can be approximated as a linear combination of the two adjacent base vectors .nu..sub.x and .nu..sub.y which are framing that sector, and either one of these two zero vectors as shown in equation 10: EQU .nu.*d.sub.x.nu..sub.x +d.sub.y.nu..sub.y +d.sub.z.nu..sub.z [10]
where: .nu..sub.z is the zero vector and d.sub.x, d.sub.y, and d.sub.z denote the duty ratios of states X, Y, and Z within one PWM cycle. The reference voltage .nu.* in FIG. 2 is located within a sector where .nu..sub.x =.nu..sub.4 and .nu..sub.y =.nu..sub.6. Therefore, the desired reference voltage can be produced by an appropriate combination of states 4 and 6, or 0 and 7. The state duty ratio is defined as the ratio of the duration to the duration of the switching interval. Therefore:
d.sub.x +d.sub.y +d.sub.z =1 [11]
With respect to vector .nu.* in FIG. 1, equation 10 can be written: EQU .nu.*=MV.sub.max e.sup.j.alpha. =d.sub.x.nu..sub.4 +d.sub.y.nu..sub.6 +d.sub.z.nu..sub.z [12]
where: M is the Modulation Index; V.sub.max =(3/2) V.sub.DC ; and .alpha. is the instantaneous angle of the motor drive. Taking V.sub.DC as the base of the calculation, the following vectors can be written as: EQU .nu..sub.x =.nu..sub.4 =1+j.sub.0 [13] EQU .nu..sub.y =.nu..sub.6 =(1/2)+j (3/2) [14] EQU V.sub.max =(3/2) [15]
Substituting from equations 13 through 15 into equation 12: EQU (3/2) M cos(.alpha.)=d.sub.x +(1/2)d.sub.y [16] EQU (3/2) M cos(.alpha.)=(3/2) d.sub.y [17]
and solving equations 15 and 16 for d.sub.x and d.sub.y : EQU d.sub.x =M sin(60.degree.-.alpha.) [18] EQU d.sub.y =M sin(.alpha.) [19]
and equation 11 provides the duration of the .nu..sub.z vector: EQU d.sub.z =1-d.sub.x -d.sub.y [20]
The simple algebraic formulas of equation 18 through 20 allow duty ratios of the consecutive logic states of an inverter to be computed in real time.